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Analysis of a multirate CT/DT cascade modulator impact of using a lowest output sampling frequency

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This paper presents the analysis of a new implementation for designing a downsampling multirate hybrid Continuous-time (CT)/discrete-time (DT) cascade ?? modulator that saves silicon area and offers a reduction of power consumption. Since the hybrid CT/DT cascade modulator has to be integrated in a standard Integrated Circuit (IC) technology, the analysis problem is formulated as a fast operation and power-efficient problem and is solved using a multirate modulator with discrete-time stages operating at the lowest sampling frequency when the input signal is downsampled. This fact enhances the operation of the continuous-time stage (i.e. front-end) to higher frequencies. The validity of the analytical models has checked by comparison with SIMSIDES software MATLAB/Simulink toolbox simulations. The match between results demonstrates that the modulator response operates according to the lower sampling frequency while the alias is properly eliminated by the Digital Cancellation Logic (DCL). In this proposal no extra analog circuits are required.

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Nowadays, wireless applications and more operation modes demand higher data rates in personal mobile devices. The efficient implementation of these devices requires power-efficient wideband Analog-to-Digital Converters (ADCs), where some ADC techniques, such as Sigma-Delta Modulators (??Ms), attempt to be a suitable solution not only for satisfying the regulations imposed by mobile applications, but also for putting into practice the usefulness of several cost functions where power consumption and high frequency operation are just a couple of several problems for the IC designer. In order to satisfy these operative regulations some mono-standard developments have been manufactured in modern Integrated Circuits (ICs) technologies. However, for multi-standard applications, few multi-standard fully-integrated CT???Ms have been reported to date [1]–[3]. This scenario invites us to take into account the Hybrid-based ?? modulator (H???M) approach, where it is assumed that these modulators take advantage of both CT and DT implementations [4]–[10]. Unfortunately, as the open literature shows, the reported H???M ICS do not exploit the capability of CT stages to operate up to the GHz range with reasonable linearity [6]–[10], because the operating difficulty is due to the maximum sampling rate being limited by the DT stages. In this new scenario, when a hybrid proposal includes both CT and DT stages, the question is: How can we contribute to satisfying the market regulations imposed on multi-standard applications? The solution proposed here is based on a downsampled process where the input stage (CT front-end) operates at the highest clock rate while maintaining the operation of the DT back-end at a low frequency. In this proposal, the goal is reached by relaxing the dynamic requirements of the back-end and meeting the required design specifications by combining different Over Sampling Ratios (OSRs) into a suitable multirate scheme [11]. This proposal was first mathematically evaluated by obtaining the overall transfer function of the ??M in the z-domain, and then properly corroborating it with high-level simulations based on SIMSIDES [12]. The correlation between results not only demonstrates the viability of the proposed architecture, but shows the design problem comprehension and also how that design problem is faced by novel designers, i.e. PhD students.

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